This work presents a hardware design for the post-quantum Hamming Quasi-Cyclic (HQC) Key Encapsulation Mechanism (KEM). We present a novel unified design allowing a runtime selection of both the cryptosystem primitive being computed (i.e., key generation, encap- sulation, and decapsulation) and the parameter set suitable to provide a security margin equivalent to the one exhibited by AES-128, AES-192, and AES-256, respectively. Despite the provided flexibility, our design improves the latency (from 1.56× to 2.38×) and efficiency (from 1.24× to 1.88×) with respect to the state of the art on a HQC hardware ac- celerator exhibiting a security margin equivalent to the one of AES-128, while providing original designs and benchmark points also for the other security margins. To the best of our knowledge, this is the first hardware design with full compliance with the HQC specification.